1. Field of the Invention
The present invention relates to an A/D converter (an analog-to-digital converter), and more particularly to an A/D converter with variable resolution suitable for a communication use.
2. Description of the Related Art
There are A/D converters of various types such as a high resolution ADC (analog-to-digital converter) used for digital processing of a speech signal and a high-speed ADC reading a signal on a hard disk. The most of them carries out an A/D conversion with a constant sample rate and a constant resolution. In late years, an ADC of a high speed and a high resolution is demanded in a communication use due to the spread of Internet. The reduction of power consumption of ADC is pursued for a battery-powered device with the ADC.
In radio communications is used a scheme to change a modulation mode as well as a transmission power according to situation. According to, for example, IEEE802.11a which is one of a wireless LAN standard, it is prescribed to use, in environment in which a noise and an interference signal are low, a modulation mode that a frequency utilization efficiency is high and a high speed transmission is possible, and to use, in environment in which much noise and interferences occur, a modulation mode which is hard to come under the influence of noise and interference although it reduces the transmission speed. In a fixed modulation mode, a resolution needed by a ADC changes according to the situation of a signal and a noise. However, a change of the required resolution becomes more remarkable when the modulation mode is changed as described above.
The variable resolution ADC is disclosed in a document 1: P. Setty et al., “A 5.75 b 350 M sample/s or 6.75 b 150 M sample/s reconfigurable flash ADC for a PRML read channel”, 1998 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 148–149, and a document 2: E. K. F. Lee. et al., “Reconfigurable data converter as a building block for mixed-signal test”, European Design and Test Conference, 1997. Proceedings, pp. 359–363. In general, it is difficult to realize a high speed and high resolution ADC. The document 1 discloses a technique for lowering a resolution in a fast operation and lowering a conversion rate at the time of a high resolution operation. The document 2 discloses the following technique. For the purpose of a test of an analog-to-digital mixed palletizing integrated circuit, a plurality of conversion stages each comprising a one-bit ADC, a D/A converter and an error amplifier are connected in cascade. The connection of the conversion stages are changed by a switch and the like to use as a DAC, a noise source or an ADC. It is necessary for reducing a power consumption to decide distribution of a current consumption according to a permission noise level as be shown in a document 3: T. B. Cho et al.,. “A 10 b, 20 M sample/s, 35 mW Pipeline A/D Converter”(IEEE Journal of Solid-State Circuits Vol. 30, No. 3, March 1995, pp. 166–172.
A method mentioned in the document 1 is effective in a flash type ADC suitable for a rapid access of a hard disk, but is not enough in resolution for a use of high speed radio communications. Actually, there is often used a pipeline type ADC that is excellent in rapidity more than the flash type ADC in a use of radio communications.
The ADC disclosed in the document 2 is a superior ADC which can execute various tests at a small tip occupation area for testing, but is not suitable for low power consumption due to a pipeline type A/D converter wherein a plurality of completely identical conversion stages are connected in cascade and always operated.